Procedural assignments occur within procedures such as always, initial, task and functions and are used to place values onto variables. The variable will hold the value until the next assignment to the same variable.
The value will be placed onto the variable when the simulation executes this statement at some point during simulation time. This can be controlled and modified the way we want by the use of control flow statements such as if-else-if, case statement and looping mechanisms.
reg [7:0] data; integer count; real period; initial begin data = 8'h3e; period = 4.23; count = 0; end always @ (posedge clk) count++;
An initial value can be placed onto a variable at the time of its declaration as shown next. The assignment does not have a duration and holds the value until the next assignment to the same variable happens. Note that variable declaration assignments to an array are not allowed.
module my_block; reg [31:0] data = 32'hdead_cafe; initial begin #20 data = 32'h1234_5678; // data will have dead_cafe from time 0 to time 20 // At time 20, data will get 12345678 end endmodule
reg [3:0] a = 4'b4; // is equivalent to reg [3:0] a; initial a = 4'b4;
If the variable is initialized during declaration and at time 0 in an initial block as shown below, the order of evaluation is not guaranteed, and hence can have either 8'h05 or 8'hee.
module my_block; reg [7:0] addr = 8'h05; initial addr = 8'hee; endmodule
reg [3:0] array [3:0] = 0; // illegal integer i = 0, j; // declares two integers i,j and i is assigned 0 real r2 = 4.5, r3 = 8; // declares two real numbers r2,r3 and are assigned 4.5, 8 resp. time startTime = 40; // declares time variable with initial value 40
Procedural blocks and assignments will be covered in more detail in a later section.
This is used to assign values onto scalar and vector nets and happens whenever there is a change in the RHS. It provides a way to model combinational logic without specifying an interconnection of gates and makes it easier to drive the net with logical expressions.
// Example model of an AND gate wire a, b, c; assign a = b & c;
Whenever b or c changes its value, then the whole expression in RHS will be evaluated and a will be updated with the new value.
This allows us to place a continuous assignment on the same statement that declares the net. Note that because a net can be declared only once, only one declaration assignment is possible for a net.
wire penable = 1;
This will override all procedural assignments to a variable and is deactivated by using the same signal with deassign . The value of the variable will remain same until the variable gets a new value through a procedural or procedural continuous assignment. The LHS of an assign statement cannot be a bit-select, part-select or an array reference but can be a variable or a concatenation of variables.
reg q; initial begin assign q = 0; #10 deassign q; end
These are similar to the assign - deassign statements but can also be applied to nets and variables. The LHS can be a bit-select of a net, part-select of a net, variable or a net but cannot be the reference to an array and bit/part select of a variable. The force statment will override all other assignments made to the variable until it is released using the release keyword.
reg o, a, b; initial begin force o = a & b; . release o; end